1. Technical Field
Embodiments of the present invention relate to a dynamic verification method and device for a processor architecture. More specifically, embodiments of the present invention relate to a dynamic verification method and device for a processor architecture which more efficiently verifies at least some of the functionality provided by the execution (EXE) unit of the processor architecture.
2. Description of the Related Art
Modern processors face growing verification and reliability challenges. These challenges are posed by increasing system micro-architecture complexity (i.e., the increasing number of transistors) and aggressive technology scaling (i.e., the decreasing size of transistors). It is becoming increasingly impossible to catch all processor design bugs in pre-silicon verification. At the same time, post-silicon verification cost is ballooning. Moreover, technology scaling leads to hardware that is more vulnerable to run-time errors post-deployment such as aging, environmentally induced hard errors, transients, and intermittent failures. “Verification” may refer to the process of determining whether a processor design is correct. Verification may be performed by a hardware-based and/or software-based checker. A “checker” is a device or method which checks for correctly executed results at runtime. If the checker is hardware-based, it may be a processor, controller, or the like. Alternatively, it may be a functional unit in a processor, controller, or the like. This approach is traditionally used when full-bit checking and correction are demanded.
To provide resilient and fault-tolerant computing, designers have adopted various techniques such as:                i. Spatial replication: An odd number of redundant modules all compute an instruction and produce a result. A voting mechanism is then employed to pick the majority result. An example of spatial replication is Triple-Modular Redundancy (R. E. Lyons and W. Vanderkulk: The use of Triple-Modular Redundancy to Improve Computer Reliability. IBM Journal. April 1962).        ii. Temporal replication: The same module is used to compute (and re-compute) an instruction and produce a result an odd number of times. A voting mechanism is then employed to pick the majority result. An example of temporal replication is AR-SMT (Eric Rotenberg: AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessor. Proceedings of Fault-Tolerant Computing Systems (FTCS). 1999).        iii. Coding: Error detecting codes such as parity bits or residue bits are employed to detect computation errors up to a certain number of bit errors. Error correcting codes may also be employed.        iv. Adaptive clocking and/or supply: The same module is used to compute (and re-compute) an instruction and produce a result an odd number of times using different voltages and/or clock frequencies. A voting mechanism is then employed to pick the majority result.        
A more recent approach is DIVA (T. M. Austin: DIVA: A Dynamic Approach to Microprocessor Verification. Journal of Instruction-Level Parallelism. May 2000. and T. M. Austin: DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design. In Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, IEEE Computer Society, Haifa, Israel, 196-207. 1999) in which a checker computes an instruction and produces a result. The checker is simpler (i.e., less complex) than the processor it is meant to check. The result from the checker is then compared to the result from the complex core processor for equality before the complex core result is committed. Even though the checker is far simpler than the core processor, the checker is nonetheless an additional, redundant execution unit. Therefore, DIVA-type approaches end up duplicating or re-implementing a substantial amount of logic such as, for example, the Arithmetic Logic Units (ALUs) in the Execution (EXE) unit.